1. Field of the Invention
This invention relates to an improved layout for fabricating silicon gate depletion and enchancement pull-up field effect transistor devices.
2. Prior Art
Several layouts are known in the prior art for silicon gate enhancement and depletion-type, pull-up field effect transistor devices. However, such prior art layouts require relatively large chip area 3, and moreover have relatively poor channel dimension tolerance. As a result, the prior art layouts are unsuitable in microcircuit applications wherein a plurality of such transistor devices are fabricated in close alignment with one another on a semiconductor wafer or chip. U.S. Pat. No. 3,699,646, incorporated herein by reference, shows a field effect transistor structure in which a polysilicon gate structure is connected directly to a diffused silicon area on the substrate.